1. Technical Field
The present invention relates to a phase-locked loop (PLL) circuit and a semiconductor integrated device having the PLL circuit.
2. Description of the Related Art
A PLL circuit comprises a voltage-controlled oscillator, a frequency divider, a phase comparator for detecting the phase difference between an internal clock signal divided by the frequency divider and a reference frequency signal, a charge pump circuit for outputting a voltage in accordance with the output of the phase comparator, and a low-pass filter.
FIG. 19 is the circuit diagram of the primary part of a conventional PLL circuit. A voltage-controlled oscillator 11, a charge pump circuit 12, and a low-pass filter (LPF) 13, all of which are included in the PLL circuit, are shown in FIG. 19.
Referring to FIG. 19, the voltage-controlled oscillator (VCO) 11 is configured to connect four differential amplifiers Amp1 through Amp4 in a ring. The differential amplifier Amp1 comprises cascade-connected p-channel MOS transistor TR11 and n-channel MOS transistor TR12; cascade-connected p-channel MOS transistor TR 13 and n-channel MOS transistor TR14; and n-channel MOS transistors TR15 which is connected between the respective sources of the n-channel MOS transistors TR12 and TR14 and a ground. The other differential amplifiers Amp2 through Amp4 are configured in the same manner. A control voltage Vcntl is provided from the low-pass filter to the voltage-controlled oscillator 11 for controlling the oscillation frequency.
The charge pump circuit 12 is constituted by a current mirror circuit and a switch circuit for charging or discharging the capacitors C5 and C6 of the low-pass filter 13.
A current proportional to the current output from a current supply I1 to a MOS transistor TR21 flows in MOS transistors TR22 and TR23, and the same current as that flowing in MOS transistor TR22 flows in MOS transistor TR24.
An UP signal for controlling the direction of increasing a control voltage is given to the gate of MOS transistor TR26 of the charge pump circuit 12, while a DOWN signal for controlling the direction of decreasing a control voltage is given to the gate of MOS transistor TR27 of the charge pump circuit 12.
When the UP signal is positive, MOS transistor TR26 is turned on to charge the capacitors C5 and C6, hence increasing the control voltage Vcntl. This causes the oscillation frequency of the voltage-controlled oscillator 11 to be higher.
When the DOWN signal is positive, the MOS transistor TR27 is turned on to discharge the charges of the capacitors C5 and C6 by way of the MOS transistor TR25, hence decreasing the control voltage Vcntl. This causes the oscillation frequency of the voltage-controlled oscillator 11 to be lower.
A technique for enabling a phase comparison of a burst digital signal in the phase comparator of a PLL circuit detecting a frequency and comparing phases is known.
Further, it is known that if the pulse width of a phase comparison signal output from a phase comparator is wide, jitter generated in a charge pump circuit is reduced.
The number of transistors incorporated in a single semiconductor device has been on the increase and the operating frequency of the device has been increasing with the miniaturization of CMOS technology. A method called power supply voltage scaling is used for a logic circuit in order to reduce the power consumption so that many logic-use integrated circuits (IC) are designed to use power supply voltages around 0.8 volts to 1.2 volts.
Although it is also desired that the above noted PLL circuit will have its power supply voltage decreased down to between 0.8 and 1.2 volts in order to reduce the power consumption, when the power supply voltage is lower the problem arises that the operable voltage range of the circuit is narrowed because the charge pump circuit 12 of the PLL circuit uses a current mirror circuit.
FIG. 20 is a diagram showing the operable range of a current mirror circuit constituted by MOS transistors in conjunction with changing power supply voltages. The threshold voltage of a MOS transistor does not change with the power supply voltage VDD and therefore a reduction thereof narrows the operable voltage range of the current mirror circuit, which reduces the operating voltage margin of the circuit. The circuit operation of a circuit cascade-connecting MOS transistors in multiple stages, such as a current mirror circuit, becomes unstable if the power supply voltage is reduced and so is the PLL circuit.